1. Field of the Invention
This invention relates generally to semiconductor memory devices and more particularly to an internal power supply voltage generating circuit for a semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices typically use an internal power supply voltage which is lower than the external power supply voltage VCC since it presents the following advantages. First, as the gate oxide layer of transistors in dynamic random access memory (DRAM) devices becomes thinner, it is difficult to ensure the reliability of transistors using the 5 V standard power supplies that have been used since the 64K DRAM generation was developed. This problem is particularly serious in DRAM devices having a density of 16M or more. Therefore, the power supply voltage VCC for 16M DRAMs is typically lowered to 3.3 V, and must be decreased even more for devices having a density of 64M or more. However, from a user's standpoint, it is desirable to maintain the same VCC over two or three generations in order to reduce costs. To overcome this problem, an internal power supply voltage, which is suitable for operating transistors in a memory device, is generated by stepping down the external power supply voltage.
Second, different internal power supplies can be used inside one memory chip, thereby allowing the chip area to be minimized.
Third, the use of an internal power supply facilitates the operation of a memory device from a battery. Since the voltage of a battery decreases with the lapse of time, a large margin in the power supply voltage VCC is required for highly integrated memory devices. Thus, the use of an internal power supply voltage generator improves the reliability of a battery operated memory device.
Fourth, the use of an internal power supply can improve the performance of a memory device. For example, if the internal power supply voltage is less than the external power supply voltage VCC, a memory chip is not affected by fluctuations in the external power supply voltage. Also, when an internal power supply is used, the voltage of the internal power supply can be actively changed to compensate for changes in temperature and processing conditions. For example, the maximum operating speed of a chip generally decreases under low voltage and high temperature conditions. However, when the internal power supply voltage has a positive temperature coefficient, the operating speed of the chip is maintained even when the temperature increases. Also, even though variations in processing conditions cause variations in the channel length or the threshold voltage of each transistor, the operating speed can be maintained by setting the internal power supply voltage to accommodate changes in processing conditions.
Semiconductor memory devices that employ internal power supply voltage generating circuits typically include an array internal power supply voltage generating circuit for driving a memory cell array and a peripheral circuit internal power supply voltage generating circuit for driving a peripheral circuit.
A typical internal power supply voltage generating circuit compares a predetermined reference voltage with each output therefrom to constantly maintain the output voltage.
FIG. 1 shows a prior art internal power supply voltage generating circuit. Referring to FIG. 1, an output signal VIVG from the internal power supply voltage generating circuit is fed back to a comparator 110 and then compared with a reference voltage VREF.
If the internal power supply voltage VIVG is higher than the reference voltage VREF, the output from the comparator 110 is high. The output from the comparator 110 is transferred to a node N103 via an inverter 101 which generates a low voltage. Accordingly, a PMOS transistor 109 in a bias portion 107 is activated. Thus, an output node N105 of the bias portion 107 is high, and a driver 130 is deactivated, thereby maintaining the internal power supply voltage at a constant level.
If the internal power supply voltage VIVG becomes lower than the reference voltage, the output from the comparator 110 goes low. This causes the level of node N103 to go high, thereby activating an NMOS transistor 111 in the bias portion 107. Thus, the NMOS transistor 111 of the bias portion 107 and a PMOS transistor 113 in a precharge portion 120 are simultaneously activated. The output voltage from the bias portion 107 at node N105 is determined by the width and length of the gate in the NMOS transistor 111 of the bias portion 107 and the PMOS transistor 113 of the precharge portion 120. Thus, the driver 130 is activated by a predetermined voltage at the node N105, thereby raising the internal power supply voltage VIVG.
During a read or write operation of the semiconductor memory device, the internal power supply voltage VIVG is transferred to a bit line when a memory cell is selected. Also, when a sensing operation of the bit line is initiated, the internal power supply voltage VIVG is supplied to a "high" line of the paired bit lines. This causes the internal power supply voltage VIVG to fall below the reference voltage VREF. The decreased internal power supply voltage is then fed back to the comparator 110 of the internal power supply voltage generating circuit which compares it with the reference voltage VREF, thereby turning on the driver 130. Accordingly, the internal power supply voltage VIVG increases. Then, when the internal power supply voltage VIVG reaches the reference voltage VREF, the driver 130 is turned off.
However, in the prior art internal power supply voltage generating circuit, the external power supply voltage VCC and the ground voltage VSS fluctuate sharply due to the abrupt activation or deactivation of the driver 130. These fluctuations affect other properties of the chip, e.g., the input voltage level, thus causing malfunctions.
Accordingly, a need remains for an internal power supply voltage generating circuit which overcomes the problems of the prior art.